The present invention relates to a semiconductor memory device; and, more particularly to a semiconductor memory device employing a row repair scheme, capable of improving a repair efficiency and obtaining a stable operation regardless of variations in external factors.
Generally, a manufacturing cost in a semiconductor memory device depends on a total yield. Therefore, for increasing the total yield, spare memory cells are inserted into the semiconductor memory device. Thus, if a specific defective memory cell is detected, the defective memory cell is replaced with the spare memory cell.
FIG. 1 is a schematic diagram showing a semiconductor memory device employing a conventional row repair scheme. For the sake of convenience, it is assumed that there are eight cell blocks.
As shown, the semiconductor memory device includes four fuse boxes 100 to 104, eight redundant word line selectors 105 to 112 and eight cell blocks BLK0 to BLK7.
Each of the cell blocks BLK0 to BLK7 includes four redundant word lines R_WL0 to R_WL3 disposed in a row direction. Each of the fuse boxes 100 to 104 includes four fuse elements, and the fuse boxes 100 to 104 generate repair signals REP_0 to REP_3, respectively. Each of the repair signals REP_0 to REP_3 corresponds to the redundant word lines R_WL0 to R_WL3. The redundant word line selectors 105 to 112 drive the redundant word lines R_WL0 to R_WL3 in response to block selection address signals BLK_ADD less than 0:7 greater than .
Hereinafter, an operation of the conventional row repair scheme will be described with reference to FIG. 1.
A row address signal is inputted to all of the fuse boxes 101 to 104, and a specific cell block is selected in response to the block selection address signals BLK_ADD less than 0:7 greater than . At this time, in case where there is no defective word line having a fail bit in the selected cell block, a normal word line is activated.
Meanwhile, in case where there is a defective word line, one of the four fuse boxes 101 to 104 is programmed to activate one repair signal. The repair signal is inputted to the redundant word line selectors 105 to 112. Then, the normal word line is inactivated and the redundant word line is activated.
If there is another defective word line, another fuse box is programmed and the defective word line is replaced with another redundant word line.
As described above, in the conventional repair scheme, the redundant word lines contained in the selected cell block are activated. Accordingly, if the number of defective word lines is greater than that, of redundant word lines, it is impossible to achieve a replacement of the defective word lines.
It is, therefore, an object of the present invention to provide a semiconductor memory device employing a row repair scheme, capable of improving a repair efficiency and obtaining a stable operation regardless of variations in external factors.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device having a plurality of cell blocks, comprising: a fuse box group, coupled to the cell blocks, for generating a repair signal in response to a row address signal; a repair signal summation means for generating a repair summation signal for controlling a repair operation in response to the repair signal; a block selection signal generation means for generating a block selection signal for selecting a cell block to be repaired in response to the repair summation signal and a block selection address signal; and a repair row decoding means for driving a redundant word line in response to the repair signal and a block selection signal.